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atmel at88sc 1616 c atmel cryptomemory , 16kbit summary datasheet features ? one of a family of nine devices with user memories from 1kbit to 256 kbit ? 16kbit (2 kbyte) eeprom user memory ? sixteen 128 - byte (1 kbit) zones ? self - timed write cycle ? single byte or 16 - byt e page write mode ? programmable access rights for each zon e ? 2 kbit configuration zone ? 37- byte otp area for user - defined codes ? 160- byte area for user - defined keys and passwords ? high security features ? 64- bit mutual authentication protocol (under license of elv a) ? encrypted checksum ? stream encryption ? four key sets for authentication and encryption ? eight sets of two 24 - bit passwords ? anti - tearin g function ? voltage and frequency monitor ? smart card features ? iso 7816 class a (5v) or class b (3v) operation ? iso 7816 -3 a synchronous t = 0 protocol (gemplus ? patent ) * ? multiple zones, key sets and passwords for multi - application use ? synchronous two - wire serial interface for faster device initialization * ? programmable 8 - byte answer -to - reset register ? iso 7816 -2 compliant modul es ? embedde d application features ? low voltage operation : 2.7v to 5.5v ? secure nonvolatile storage for sensitive system or user informatio n ? two - wire serial interface ? 1.0 mhz compatibility for fast operation ? standard 8 - lead plastic packages, green compliant (ex ceeds rohs) ? same pinout as two - wire serial eeproms ? high reliability ? endurance: 100,000 cycles ? data retention : 10 years ? esd protection : 4,000v min * note: modules available with either t=0 / two - wire modes or two - wire mode only 2030ls ? crypto ? 1 2 /11 this is a summary document. the complete document is available on the atmel website at www.atmel.com.
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 2 table 1. pin assignment pad descri ption iso module twi module standard package pin v cc supply voltage c1 c1 8 gnd ground c5 c5 4 scl/clk serial clock input c3 c3 6 sda/io serial data input/output c7 c7 5 rst reset input c2 nc nc figure 1. pin configuration v cc =c1 rst=c2 scl/clk=c3 nc=c4 iso smart card module c5=gnd c6=nc c7=sda/io c8=nc nc nc nc gnd 1 2 3 4 8 7 6 5 8-lead soic, pdip v cc nc scl sda v cc =c1 nc=c2 scl/clk=c3 nc=c4 twi smart card module c5=gnd c6=nc c7=sda/io c8=nc 1. description the atmel ? at8 8sc1616c member of the atmel cryptomemory ? family is a high - perform ance secure memory providing 16 kbits of user memory with advanced security and cryptographic features built in. the user memory is divided into 16 128- byte zones, each of which may be indi vidually set with different security access rights or effectively combined together to provide space for 1 to 16 data files. 1.1 smart card applications the at88sc1616c provides high security, low cost, and ease of implementation without the need for a micropr ocessor operating system. the embedded cryptographic engine provides for dynamic and symmetric mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. up t o four unique key sets may be used for these operations. the at88sc1616c offers the ability to communicate with virtually any smart card reader using the asynchronous t = 0 protocol (gemplus patent) defined in iso 7816 - 3 . 1.2 embedded applications through dyna mic and symmetric mutual authentication, data encryption, and the use of encrypted checksums, the at88sc1616c provides a secure place for storage of sensitive information within a system. with its tamper detection circuits, this information remains safe ev en under attack. a two - wire serial interface running at 1.0 mhz is used for fast and efficient communications with up to 15 devices that may be individually addressed. the at88sc1616c is available in industry standard 8 - lead packages with the same familiar pinout as two - wire serial eeproms .
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 3 figure 1 -1. block diagram random generator authentication, encryption and certification unit eeprom answer to reset data transfer password verification reset block asynchronous iso interface synchronous interface power management v cc gnd scl/clk s d a/io rst 2. pin descriptions 2.1 supply voltage (v cc ) the v cc input is a 2.7v to 5.5v positive voltage supplied by the host. 2.2 clock (scl/clk) in the asynchronous t = 0 protocol, the scl/clk input is used to provide th e device with a carrier frequency f . the nominal length of one bit emitted on i/o is defined as an ?elementary time unit? (etu) and is equal to 372/ f . when the synchronous protocol is used, the scl/clk input is used to positive edge clock data into the dev ice and negative edge clock data out of the device. 2.3 reset (rst) the at88sc1616c provides an iso 7816 - 3 compliant asynchronous answer to reset sequence. when the reset sequence is activated, the device will output the data programmed into the 64 - bit answe r-to - reset register. an internal pull - up on the rst input pad allows the device to be used in synchronous mode without bonding rst. the at88sc1616c does not support the synchronous answer -to - reset sequence. 2.4 serial data (sda/io) the sda pin is bidirectiona l for serial data transfer. this pin is open - drain driven and may be wired with any number of other open drain or open collector devices. an external pull - up resistor should be connected between sda and v cc . the value of this resistor and the system capaci tance loading the sda bus will determine the rise time of sda. this rise time will determine the maximum frequency during read operations. low value pull - up resistors will allow higher frequency operations while drawing higher average power. sda/io informa tion applies to both asynchronous and synchronous protocols. when the synchronous protocol is used, the scl/clk input is used to positive edge clock data into the device and negative edge clock data out of the device .
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 4 3. *absolute maximum ratings operating temperature .................... ? 40c to +85c storage temperature ................... ? 65c to + 150c voltage on any pin with respect to ground ............... ? 0.7 to v cc +0.7v maximum operating voltage ............................. 6.0v dc output current ......................................... 5.0ma * notice : stresses beyond those listed under ?absolute maximum ratings? m ay cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maxim um rating conditions for extended periods of time may affect device reliability. table 3 -1. dc characteristics applicable over recommended operating range from v cc = +2.7 to 5.5v, t ac = -40 c to +85c ( unless otherwise noted ) symbol parameter test condition min t yp max units v cc (2) supply voltage 2.7 5.5 v i cc supply current (v cc = 5.5v) async read at 3.57mhz 5 ma i cc supply current (v cc = 5.5v) async write at 3.57mhz 5 ma i cc supply current (v cc = 5.5v) synch read at 1mhz 5 ma i cc supply current (v cc = 5.5v) synch write at 1mhz 5 ma i sb standby current (v cc = 5.5v) v in = v cc or gnd 1 00 a v il (1) sda/io input low threshold 0 v cc x 0.2 v v il (1) scl/clk input low threshold 0 v cc x 0.2 v v il (1) rst input low threshold 0 v cc x 0.2 v v ih (1)(2 ) sda/io input high threshold v cc x 0.7 v cc v v ih (1)(2) scl/clk input high threshold v cc x 0.7 v cc v v ih (1)(2) rst input high threshold v cc x 0.7 v cc v i il sda/io input low current 0 < v il < v cc x 0.15 15 a i il scl/clk input low current 0 < v i l < v cc x 0.15 15 a i il rst input low current 0 < v il < v cc x 0.15 50 a i ih sda/io input high current v cc x 0.7 < v ih < v cc 20 a i ih scl/clk input high current v cc x 0.7 < v ih < v cc 100 a i ih rst input high current v cc x 0.7 < v ih < v cc 1 50 a v oh sda/io output high voltage 20k ohm external pull - up v cc x 0.7 v cc v v ol sda/io output low voltage i ol = 1ma 0 v cc x 0.15 v i oh sda/io output high current v oh 20 a notes: 1. v il min and v ih max are re ference only and are not tested 2. to prevent l atch up conditions from occurring during power up of the at88scxxxxc, v cc must be turned on before applying v ih . fo r powering dow n, v ih must be removed before turning v cc off
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 5 table 3 -2. ac characteristics applicable over recommended operating range from v cc = +2.7 to 5.5v, t ac = - 40c to +85c, cl = 30pf ( unless otherwise noted) symbol parameter min max units f clk async clock frequency (v cc range: +4.5 - 5.5v) 1 5 mhz f clk async clock frequency (v cc range: +2.7 - 3.3v) 1 4 mhz f clk synch clock frequency 0 1 mhz clock duty cycle 40 60 % t r rise time - i/o, rst 1 s t f fall time - i/o, rst 1 s t r rise time - clk 9% x period s t f fall time - clk 9% x period s t aa clock low to data out valid 35 ns t hd.sta start hold time 200 ns t su.sta start set -up time 200 ns t hd.dat data in hold time 10 ns t su.dat data in set - up time 100 ns t su.sto stop set - up time 200 ns t dh data out hold time 20 ns t wr write cycle time (at 25 c) 5 ms t wr write cycle time ( -40 to +85 c) 7 ms 4. device operat ion f or synchronous protocols c lock and data transitions : the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 4 - 3 on page 7 ). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high -to - low transition of sda with scl high is a start condition which must precede any other command (see figure 4 -4 on page 7 ). stop condition: a low -to - high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mod e (see figure 4 -4 on page 7 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8 - bit words. the eeprom sends a zero to acknowledge that it has received each word. this happens during the ninth clock cycle (see figure 4 -5 on page 7 ). memory reset: after an interruption in protocol, p ower loss or system reset, any two - wire part ca n be reset by following these steps: 1. clock up to nine cycles 2. look for sda high in each cycle while scl is high 3. create a start condition
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 6 figure 4 -1. bus timing for two - wire c ommunic ations scl: serial clock, sda ? serial data i/o scl sd a in sd a out t f t high t lo w t lo w t r t aa t dh t b uf t su .s t o t su .d a t t hd .d a t t hd .s t a t su .s t a figure 4 -2. write cycle timing: scl serial clo ck, sda ? serial data i/o t wr (1) st op condition st ar t condition w ordn a ck 8th bit scl sd a note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 7 figure 4 -3. data validity data change allowed data stable data stable sda scl figure 4 -4. start and stop definitions sd a scl start stop figure 4 -5. output acknowledge scl d a t a in d a t a out e g d e l w o n k c a t r a t s 9 8 1
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 8 5. device architecture 5.1 user zon es the eeprom user memory is divided into 16 zones of 1024 bits each. multiple zones allow for different types of data or files to be stored in different zones. access to the user zones is allowed only after security requirements have been met. these secur ity requirements are defined by the user during the personalization of the device in the configuration memory. if the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone . figure 5 -1. user zones zo ne $0 $1 $2 $3 $4 $5 $6 $7 user 0 $00 128 b ytes $78 user 1 user 14 $00 $78 user 15 $00 128 b ytes $78 6. control logic access t o the user zones occurs only through the control logic built into the device. this logic is configurable through access registers, key registers and keys programmed into the configuration memory during device personalization. also implemented in the contro l logic is a cryptographic engine for performing the various higher - level security functions of the device.
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 9 7. configuration memory the configuration memory consists of 2048 bits of eeprom memory used for storing passwords, keys and codes and for defining security levels to be used for each user zone. access rights to the configuration memory are defined in the control logic and may not be altered by the user. figure 7 -1. configuration memory $0 $1 $2 $3 $4 $5 $6 $7 $00 answer to reset identification $08 fab code mtz card manufacturer code $10 lot history code read only $18 dcr identification number nc access control $20 ar0 pr0 ar1 pr1 ar2 pr2 ar3 pr3 $28 ar4 pr4 ar5 pr5 ar6 pr6 ar7 pr7 $30 ar8 pr8 ar9 pr9 ar10 pr10 ar11 pr11 $38 ar12 pr12 ar13 pr13 ar14 pr14 ar15 pr15 $40 issuer code $48 $50 for authentication and encryption use cryptography $58 $60 $68 $70 $78 $80 $88 $90 for authentication and encryption use secret $98 $a0 $a8 $b0 pac write 0 pac read 0 p assword $b8 pac write 1 pac read 1 $c0 pac write 2 pac read 2 $c8 pac write 3 pac read 3 $d0 pac write 4 pac read 4 $d8 pac write 5 pac read 5 $e0 pac write 6 pac read 6 $e8 pac write 7 pac read 7 $f0 reserved forbidden $f8
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 10 8. security fus es there are three fuses on the device that must be blown during the device personalization process. each fuse locks certain portions of the configuration memory as otp memory. fuses are designed for the module manufacturer, card manufacturer and card issu er and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step . 9. protocol selection the at88sc1616c supports two different communication protocols. ? smart card applications : the asynchr onous t = 0 protocol defined by iso 7816 - 3 is used for compatibility with the industr y?s standard smart card readers ? embedded applications : a two - wire serial interface is used for fast and efficient communic ation with logic or controllers the power - up sequ ence determines which of the two communication protocols will be used. 9.1 asynchronous t = 0 protocol this power - up sequence complies with iso 7816- 3 for a cold reset in smart card applications. ? v cc goes high; r st, i/o - sda and clk - scl are low ? set i/o - sda in r eceive mode ? pr ovide a clock signal to clk - scl ? rst goes high after 400 clock cycles the device will respond with a 64 - bit atr code, including historical bytes to indicate the memory density within the cryptomemory family. once the asynchronous mode has bee n selected, it is not possible to switch to the synchronous mode without powering off the device. figure 9 -1. asynchronous t = 0 protocol (gemplus patent) v cc i/o-s d a rst clk-scl a tr
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 11 9.2 synchronous two - wire serial interface the synchronous mode is the default after powering up v cc due to a n internal pull - up on rst. for embedded applications using cryptomemory in standard plastic packages, this is the only communication protocol. ? power - up v cc , rst goes high also ? after stable v cc , cl k - scl and i/o - sda may be driven figure 9 -2. synchronous two - wire protoco l v cc i/o-s d a rst clk-scl 1 2 3 4 5 note: five clock pulses must be sent before the first command is issued 10. communication security modes communications between the device and host operate in three basic modes. standard mode is the default mode for the device after power - up. authentication m ode is activated by a successful authentication sequence. encryption mode is activated by a successful encryption activation following a successful authentication . table 10 -1. communication security modes (1) mode configuration data user data passwords data integrity c heck standard clear clear clear mdc authentication clear clear encrypted mac encryption clear encrypted encrypted mac notes: 1. configuration data include viewable areas of the configuration zone except the passwords: ? m dc: modification detection code ? m ac: me ssage authentication code
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 12 11. security options 11.1 anti - tearing in the event of a power loss during a write cycle, the integrity of the device?s stored data may be recovered. this function is optional ? the host may choose to activate the anti - tearing f unction, depending on application requirements. when anti - tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data are limited to eight bytes. data are written first to a buffer zone in eepro m instead of the intended destination address, but with the same access conditions. the data are then written in the required location. if this second write cycle is interrupted due to a power loss , the device will automatically recover the data from the s ystem buffer zone at the next power - up. in two - wire mode, the host is required to perform ack polling for up to 8 ms after write commands when anti - tearing is active. at power - up, the host is required to perform ack pol ling, in some cases for up to 2 ms , in the event that the device needs to carry out the data recovery process . 11.2 write lock if a user zone is configured in the write lock mode, the lowest address byte of an 8 - byte page constitutes a write access byte for the bytes of that page. example: the write lock byt e at $080 contr ols the bytes from $080 to $087 table 11 -1. write lock example address $0 $1 $2 $3 $4 $5 $6 $7 $08 0 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx locked locked locked the write lock byte may also be locked by w riting its least significant (rightmost) bit to ?0?. moreover, when write lock mode is activated, the write lock byte can only be programmed ? that is, bits written to ?0? cannot return to ?1?. in the write lock configuration, only one byte can be written at a time. even if several bytes are received, only the first byte will be taken into account by the device .
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 13 12. password verification passwords may be used to protect read and/or write access of any user zone. when a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or rst becomes active. there are eight password sets that may be used to protect any user zone. only one password is active at a time, but write passwords give read a ccess also . 12.1 authentication protocol the access to a user zone may be protected by an authentication protocol. any one of four keys may be selected to use with a user zone. the authentication success is memorized and active as long as the chip is powered, u nless a new authentication is initialized or rst becomes active. if the new authentication request is not validated, the card loses its previous authentication and it should be presented again. only the last request is memorized. note: password and authenticat ion may be presented at any time and in any order. if the trials limit has been reached (after four consecutive incorrect attempts), the password verification or authentication process will not be taken into account figure 12 -1. password and authentication operations device (card) card number verify a compute challenge b challenge b verify rpw data checksum (cs) verify wpw verify cs write data host (reader) compute challenge a challenge a verify b read password (rpw) verify cs write password (wpw) data cs authentication read access write access
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 14 12.2 checksum the at88sc1616c implements a data validity check function in the form of a checksum, which may function in standard, authentication or encryption modes. in the standard mode, the checksum is implemented as a modification detection code (mdc), in which the host may read an mdc from the device in order to verify that the data sent was received correctly. in the authentication and encryption modes, the checksum becomes more powerful since it provides a bidirectional data integrity check and data origin authentication capability in the form of a message authentication code (mac). only the host/device that carried out a valid authentication is capable of computing a valid mac. while operating in the authenticatio n or encryption modes, the use of a mac is required. for an ingoing command, if the device calculates a mac different from the mac transmitted by the host, not only is the command abandoned but the mode is also reset. a new authentication and/or encryption activation will be required to reactivate the mac. 12.3 encryption the data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. the issuer may choose to require encryption for a user zone by settings mad e in the configuration memory. any one of four keys may be selected for use with a user zone. in this case, activation of the encryption mode is required in order to read/w rite data in the zone and only encrypted data will be transmitted. even if not requi red, the host may elect to activate encryption provided the proper keys are known . 12.4 supervisor mode enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including th e ability to change passwords. 12.5 m odify forbidden no write access is allowed in a user zone protected with this feature at any time. the user zone must be written during devic e personalization prior to blowing the security fuses. 12.6 program only for a user zone protected by this feature, data within the zone may be changed from a ?1? to a ?0?, but never from a ?0? to a ?1?. 13. initial device programming to enable the security features of cryptomemory, the device must first be personalized to set up several registers and load i n the appropriate pa sswords and keys. this is accomplished through programming the configuration memory of cryptomemory using simple write and read commands. to gain access to the configuration memory, the secure code must first be successfully presented. for the at88sc1616c device, the secure code is $20 0c e0. after writing and verifying data in the configuration memory, the security fuses must be blown to lock this information in the device. for additional information on personalizing cryptomemory, please see the applicatio n notes programming cryptomemory for embedded applications and initializing cryptomemory for smart card applications (at www.atmel.com ).
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 15 14. ordering information atmel ordering code package voltage range temperature ra nge at88sc1616c -mj at88sc1616c -mp at88sc1616c -mj tg at88sc1616c -mp tg m2 ? j module ? iso m2 ? p module - iso m2 ? j module ? twi m2 ? p module - twi 2.7v ? 5.5v commercial (0c ? 70c) at88sc1616c -pu at88sc1616c -sh 8p3 8s1 2.7v ? 5.5v green compliant (exceeds r ohs) industrial ( ?40c ? 85c) at88sc1616c -wi 7 mil wafer 2.7v ? 5.5v industrial ( ? 40c ? 85c) package type (1) (2) description m2 ? j module : iso or twi m2 iso 7816 smart card module m2 ? p module : iso or twi m2 iso 7816 smart card module wi th atmel ? logo 8p3 8 - lead, 0.300? wide , plastic dual inline (pdip) 8s1 8 - lead, 0.150? wide , plastic gull wing small outline (jedec soic) notes: 1. formal drawings may be obta ined from an atmel sales office 2. both the j and p module packages are used for eith er iso (t=0 / 2 - wire mode) or twi (two - wire mode only)
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 16 15. packaging information ordering code: mj or mjtg ordering code: mp or mptg module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: round - ? 8.5 [mm] thickness: 0.58 [mm] pitch: 14.25 mm mod ule size: m2 dimension*: 12.6 x 11.4 [mm] glob top: square - 8.8 x 8.8 [mm] thickness: 0.58 [mm] pitch: 14.25 mm note: * the module dimensions listed refer to the dimensions of the exposed metal contact area. the actual dimensions of the module after exci se or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e., a punched m2 mo dule will yield 13.0 x 11.8mm)
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 17 15.1 ordering code: sh 8s1 ? jedec soic package drawing contact: packagedrawings@atmel.com dra wing no . rev . title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view 8s1 g 6/22/11 notes: this drawing is for general information onl y . refer to jedec drawing ms-012, v ariation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 18 15.2 ordering code: pu 8p3 ? pdip package drawing contact: packagedrawings@atmel.com dr a wing n o . re v . title gpc notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, v ariation b a for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0. 1 15 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc e a 0.300 bsc 4 l 0. 1 15 0.130 0.150 2 top view side view end view 8p3 d 06/21/11 8p3, 8-lead, 0.300? wide bod y , plastic dual in-line package (pdip) ptc
atmel at88sc 1616 c [ summary datasheet ] 2030ls ? crypto ? 1 2 /11 19 16. revision history doc. rev. date comments 2030l s 12 /2011 update template update package drawings change at88sc 1616 c -s u to at88sc 1616 c -sh 2030ks 10 /2009 features section ? add ?green compliant (exceeds rohs) to end of ?standard 8 - lead plastic packages? bullet added note to dc characteristics table and applied to v cc and all 3 in stances of vih symbols in table ordering information page: add ?green compliant (exceeds rohs) to middle row of temperature range replace ?lead - free/halogen- free. keep industrial updated to 2009 copyright sb - twi package update 2030js 11/2008 removed p module offering 2030is 04/ 2007 updated timing diagrams 2030is 01 /2007 final release version 2030is 01/2007 replaced user zone, configuration memory, and write lock exam ple tables with new information
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